VLSI Design – Digital System: VLSI DESIGN FLOW
The main focus of this blog is to provide information on various VLSI design languages like VHDL, Verilog, System Verilog, UVM, etc. VLSI is one of the most growing industries in today’s world. It offers great exposure and opportunities to both frontend and backend people. Many people look for various topics in this field but the data is not readily available online. So, by this blog, we focus to provide information about all the languages in a simple language and with as many examples as possible.
VLSI (Very Large Scale Integration) is the process of creating an IC (Integrated Circuit). VLSI is broadly classified into two parts-
- Front-end: In frontend, we deal
withtheDesign and Verification of the chip. It includes designing (using either VHDL/Verilog/SystemVerilog) and verification( using Verilog/System Verilog/UVM test bench) of thedesignto meet the desired functionality. The HDL code is repeatedly simulated ,synthesizedand updated until it meets the design specification. It also dealswithmeeting the timing constraints/requirements for the design and Synthesisofthe design.
- Back-end: In
backend, we deal withthephysical design part of the chip. The design made in front-end isfabricatedand manufactured here, i.e., the design is developed in hardware .Aftermanufacturing, the design is again simulated and verified for thefunctionality.
VLSI DESIGN FLOW OVERVIEW:
- Design Specification: It describes the desired functionality of the circuit to be designed.
BehavioralDescription: It is created to analyze the design in terms of functionality, performance, compliance to standards, andotherhigh-level issues. It is often written with HDLs.
- RTL Description (HDL): The
behavioraldescription is converted into RTL description by coding in HDL for the desired functionality.
- Functional verification and testing: The HDL code is verified and tested repeatedly to achieve the desired functionality.
- Logic synthesis and timing verification: The HDL code is synthesized and timing analysis of the synthesized design is done to achieve the desired timing requirements.
- Gate-level netlist: It is a description of
circuitin terms of gates and connections between them.
- Logical verification and testing: The logic of the circuit is again verified and tested for functionality by using the netlist in place of RTL code.
- Floor planning and place and route: The required area of the chip die, the core area within the die where it is permitted to place the synthesized design, area for blockages where no cell should be placed etc are determined in floor planning. The actual location of the instances of the standard cells
tobeplaced in the core area of the die and the path through which cells areconnectedon 2D and 3D plane is determined for the entire design in placeandroute.
- Physical layout
: Thephysical layout of thechipis obtained in this with the help of various tools.
- Layout verification: The layout is checked for
thepresenceof any Design Rule Violation (DRC).
- Implementation: The physical layout is used
toimplementthe design in order to generate it in hardware.